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| P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM FEATURES VCC Current (Commercial/Industrial) -- Operating: 70mA/85mA -- CMOS Standby: 100A/100A Access Times --55/70 (Commercial or Industrial) Single 5 Volts 10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --32-Pin 600 mil Plastic and Ceramic DIP --32-Pin 445 mil SOP --32-Pin TSOP DESCRIPTION The P4C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The P4C1024L is packaged in a 32-pin TSOP, 445 mil SOP, and a 600 mil PDIP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (P600, C10), SOP (S12) TOP VIEW See end of datasheet for TSOP pin configuration. Document # SRAM125 REV C Revised September 2006 1 P4C1024L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0C to 70C) Industrial (-40C to 85C) Supply Voltage 4.5V VCC 5.5V 4.5 VCC 5.5V MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V C C mA mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Symbol VOH VOL VIH VIL ILI ILO ISB Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) GND VIN VCC GND VOUT VCC CE1 VIH or CE2 VIL VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL VCC = 5.5V, IOUT = 0 mA CE1 VCC -0.2V, CE2 0.2V Ind'l. Com'l. Ind'l. Com'l. Test Conditions IOH = -1mA, VCC = 4.5V IOL = 2.1mA 2.2 -0.5 -5 -2 -5 -2 Min 2.4 0.4 VCC + 0.3 0.8 +5 +2 +5 +2 3 Max Unit V V V V A A mA ISB1 100 A Document # SRAM125 REV C Page 2 of 10 P4C1024L CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Industrial * -55 70 85 -70 70 85 -55 15 25 ** -70 15 25 Unit mA mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 VIH (min), CE1 and WE VIL (max), OE is high. Switching inputs are 0V and 3V. **As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 55 5 20 0 70 -55 Min 55 55 55 5 10 20 30 5 25 5 10 25 35 Max Min 70 70 70 -70 Max Unit ns ns ns ns ns ns ns ns ns ns ns Document # SRAM125 REV C Page 3 of 10 P4C1024L READ CYCLE NO. 1 (OE CONTROLLED)(1) OE READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CE CONTROLLED) CE Notes: 1. WE is HIGH for READ cycle. 2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. 4. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM125 REV C Page 4 of 10 P4C1024L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 5 -55 Min 55 50 50 0 40 0 25 0 25 5 Max Min 70 60 60 0 50 0 30 0 30 -70 Max Unit ns ns ns ns ns ns ns ns ns ns WRITE CYCLE NO. 1 (WE CONTROLLED)(6) WE Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM125 REV C Page 5 of 10 P4C1024L TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6) CE AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Fig. 1 and 2 TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CE1 CE2 OE WE H X L L L X L H H H X X H L X X X H H L I/O High Z High Z High Z DOUT DIN Power Standby Standby Active Active Active Figure 1. Output Load * including scope and test fixture. Figure 2. Thevenin Equivalent Note: Because of the high speed of the P4C1024L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.77V (Thevenin Voltage) at the comparator input, and a 589 resistor must be used in series with DOUT to match 639 (Thevenin Resistance). Document # SRAM125 REV C Page 6 of 10 P4C1024L DATA RETENTION Symbol VDR ICCDR (1) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time Test Conditions CE1 VCC -0.2V, CE2 0.2V, VIN VCC -0.2V or VIN 0.2V VDR = 2.0V VDR = 3.0V See Retention Waveform 0 5 Min 2.0 Max 5.5 30 50 Unit V A A ns ms tCDR tR 1. CE1 VDR -0.2V, CE2 VDR -0.2V or CE2 0.2V; or CE1 0.2V, CE2 - 0.2V; VIN VDR -0.2V or VIN 0.2V LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED) CE LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED) DATA RETENTION MODE VCC 4.5V VDR CE2 -0.2V 4.5V tCDR CE2 VIL 2.2V tR VIL Document # SRAM125 REV C Page 7 of 10 P4C1024L ORDERING INFORMATION SELECTION GUIDE The P4C1024L is available in the following temperature, speed and package options. Temperature Range Commercial Package Plastic DIP (600 mil) Plastic SOP (445 mil) TSOP Ceramic DIP (600 mil) Industrial Plastic DIP (600 mil) Plastic SOP (445 mil) TSOP Ceramic DIP (600 mil) Speed -55 -55PC -55SC -55TC -55CWC -55PI -55SI -55TI -55CWI -70 -70PC -70SC -70TC -70CWC -70PI -70SI -70TI -70CWI TSOP PIN CONFIGURATION Document # SRAM125 REV C Page 8 of 10 P4C1024L Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P600 32 (600 mil) Min Max 0.170 0.210 0.015 0.014 0.023 0.045 0.070 0.009 0.014 1.600 1.400 0.530 0.300 0.600 0.380 0.100 BSC 0.600 BSC 0.120 0.150 0 15 PLASTIC DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 b2 C D e E H h L S12 32 (445 Mil) Min Max 0.118 0.004 0.014 0.020 0.006 0.012 0.790 0.820 0.050 BSC 0.435 0.455 0.546 0.566 0.010 0.029 0.023 0.039 0 8 SOIC/SOP SMALL OUTLINE IC PACKAGE Document # SRAM125 REV C Page 9 of 10 P4C1024L Pkg # # Pins Symbol A A2 b D E e HD T3 32 Min Max 0.048 0.037 0.042 0.006 0.011 0.720 0.729 0.307 0.323 0.050 BSC 0.779 0.796 TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm) Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C10 32 (600 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.680 0.510 0.620 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - SIDEBRAZED DUAL IN-LINE PACKAGES Document # SRAM125 REV C Page 10 of 10 P4C1024L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C ISSUE DATE 1997 Oct-05 Feb-06 Sep-06 SRAM125 P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM ORIG. OF CHANGE DAB JDB JDB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added TSOP package Added Ceramic DIP package Document # SRAM125 REV C Page 11 of 10 |
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